United States

Vanadium dioxide (VO2) has been widely studied for its prominent insulator-metal transition (IMT) near room temperature and potential applications in novel memory devices and brain-inspired neuromorphic computing. We report on the fabrication of in-plane VO2 metal-insulator-metal (MIM) structures and reproducible switching measurements in these two-terminal devices. The VO2 film grown on TiO2 (001) substrate by pulsed laser deposition (PLD) was etched into bridge structures with different sizes. Resistive switching can be achieved by applying current/voltage bias, which creates Joule heating in the device and triggers the IMT. We observe repeatable volatile switching and a clear correlation between the switching power and device size. Here, we also report that our memory element is capable of multi-level storage in a single cell. By adjusting the compliance and voltage bias, we are able to freely and reliably move between these intermediate levels. This approach provides a gateway to mimic neurons and synapses with hardware components, allowing for much denser and complex neural networks.

Materials Challenges for Memory

Multi-level operation in VO2 resistive switching devices

memristor

resistive switching

[![](https://assets.underline.io/uploads/markdown_image/1/image/985c8a40b04e56675221c8549975de3c.png)](https://drive.google.com/file/d/1B70nPIeeeqdG4UU70NlYXuKVOHLRuJEo/view?usp=sharing)

### ** History of DRC**
The Device Research Conference (DRC) began in the pre-transistor era with the 1942 establishment of the Conference on Electron Device Research (CEDR). Following William Shockley’s 1948 CEDR presentation of the transistor device, the Solid-State Device Research Conference (SSDRC) was established, with invitation-only attendance.

In the ensuing decades, many exciting firsts were presented at SSDRC, including the use of impurity diffusion in silicon and germanium, the first practical MOSFET, and the first lattice-matched heterojunction.

In 1969, under the leadership or Herbert Kroemer and Cal Quate, the CEDR and SSDRC merged into DRC. In 1970, attendance was opened to all, and the first DRAM (dynamic random-access memory), room temperature lasers, and first CCD (charge-coupled device) were reported—all in the same 1970 DRC meeting!

1976 saw the first official coordination of tandem meetings between DRC and the Electronic Materials Conference (EMC) to bring together the electronic materials and device communities—a custom which persists to this day. In 1991, DRC began publishing its digest with IEEE; they can all be found [here on IEEE Xplore](https://ieeexplore.ieee.org/xpl/conhome/1000199/all-proceedings). Throughout this period, DRC featured reports of many novel and record-setting devices, including the HEMT (High Electron Mobility Transistor), VCSEL (Vertical Cavity Surface Emitting Laser), HBT (Heterojunction Bipolar Transistor), and nanoscale MOSFETs.

In recent years, DRC has continued to be the world’s premier forum to present innovative semiconductor device research with work on organic thin film transistors, graphene and carbon nanotube transistors, and 2D materials all featuring prominently in the 1990s through to the present day. In 2017, we celebrated DRC’s 75th anniversary with special sessions and an [article in the Journal of the Electron Device Society](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8168249&isnumber=8232486). DRC technical topics continue to evolve with emerging device trends such as memory devices, quantum devices, optoelectronics/photonics, and wide bandgap power devices to reflect the exciting work being done by a diverse community of device engineers around the globe.

Today, as we look forward to the next 75+ years of device innovation, DRC continues to lead the way in showcasing top-caliber research, facilitating vibrant discussion and debate and acting as a platform to nurture the next generation of device engineers. We welcome you to join us at the next DRC!

To learn more about DRC's history, please see [Aaron Franklin, Debdeep Jena and Deji Akinwande, "75 Years of the Device Research Conference—A History Worth Repeating," in IEEE Journal of the Electron Devices Society, vol. 6, pp. 116-120, 2018. doi: 10.1109/JEDS.2017.2780778](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8168249&isnumber=8232486).

### **Topics**
* Biological Devices
* Devices for Extreme Conditions
* Heterogeneously Integrated Devices
* Memory Devices
* Modeling and Simulation of Devices
* Nanoscale and Vacuum Devices
* Optoelectronic and Optical Devices
* Other Emerging Devices
* Power Devices
* Quantum Devices
* RF and Terahertz Devices
* Spintronic and Magnetic Devices
* Thin-film Devices
* Wide-bandgap Devices
 
### **Invited Speakers**
* Patrick Fay, University of Notre Dame
* Susanne Hoffmann-Eifert, Peter Grünberg Institute
* Sanghyeon Kim, Korea Advanced Institute of Science and Technology
* Sriram Krishnamoorthy, University of California, Santa Barbara
* Mario Lanza, King Abdullah University of Science and Technology
* Xiuling Li, The University of Texas at Austin
* Marko Radosavljevic, Intel Corporation
* Siddharth Rajan, The Ohio State University
* Giordano Scappucci, Delft University of Technology
* Fisher Yu, University of Arkansas
* Wenjuan Zhu, University of Illinois at Urbana-Champaign




Registration is required to attend this event. If you have not already done so, please use the link below to register for a ticket to the conference:

https://www.mrs.org/drc-2022/registration

Registration Is Required

DRC 2022

DRC continues to be the world’s premier forum to present innovative semiconductor device research with work on organic thin film transistors, graphene and carbon nanotube transistors, and 2D materials all featuring prominently in the 1990s through to the present day. In 2017, we celebrated DRC’s 75th anniversary with special sessions and an article in the Journal of the Electron Device Society. 
DRC technical topics continue to evolve with emerging device trends such as memory devices, quantum devices, optoelectronics/photonics, and wide bandgap power devices to reflect the exciting work being done by a diverse community of device engineers around the globe.

poster


![](https://assets.underline.io/uploads/markdown_image/1/image/2e10c515564e9ec3287ee4c664011c20.png)

The energy cost of storing and moving data is enormous, and is growing at such a rapid pace that within a few years the power demand may overwhelm some developed nations. Non-volatile memory (NVM) and neuromorphic computing are enabling critical advances in this area, but there are many scientific and technological challenges. This conference will cover the materials challenges of different memory technologies, from the fundamental processes and mechanisms, to industry perspectives on materials specifications and manufacturing.

Magnetoelectric materials have very broad prospects in sensors, next-generation memory devices, etc. However, the practical application of magnetoelectric exchange films is still challenged by many factors, such as the substrate clamping effect, the leakage problem, and the large bias field. In response to the above challenges, we have taken the following three measures. First, we adopted a vertically aligned nanocomposite (VAN) structure instead of the traditional multilayer structure to overcome the substrate clamping effect and achieve an efficient strain coupling. Secondly, we chose the less leaky Na0.5Bi0.5TiO3 instead of BiFeO3 as the ferroelectric matrix. A p-n junction formed at the film-substrate interface, which further suppressed the vertical leakage current in the nanocomposite film. The low leakage enables the in-situ electric field control of magnetic properties in the ultra-thin multiferroic composite film in a large scale. In the Na0.5Bi0.5TiO3 -CoFe2O4 VAN, the obtained magnetoelectric coefficient is as high as 1.32x10-9 s m-1. Finally, we introduced the antiferromagnetic phase, i.e. NiO, into the traditional ferrimagnetic-ferroelectric two-phase multiferroic composite film to form a three-phase Na0.5Bi0.5TiO3-NiO-NiFe2O4 VAN film, where a self-biased magnetoelectric effect was achieved via the antiferromagnetic-ferromagnetic exchange coupling. These studies have paved the way to the practical application of composite multiferroic thin films in electronic devices, such as magnetoelectric random memory (MeRAM).

Approach to the practical magnetoelectrics with the vertically aligned nanocomposites

In this work we investigate the effect of annealing in different atmospheres (inert: Ar; and reducing: H₂/N₂) towards optimising the electrical operation of Pt/TiOx/Pt devices. Overall, annealed devices exhibit lower operating voltages and more prominent hysteretic behaviour. Additionally we are exploring the effect of the process in both the crystalline structure of said devices as well as on the top Pt/TiOx interface. By carefully tuning the annealing temperature and conditions we can transition from an amorphous film to a microcrystalline and subsequently to a fully crystalline one with pronounced characteristic anatase peaks.


Interface effects of annealing processes on TiO2-based memristive devices

A metal barrier layer (BL) is usually inserted between the top electrode and oxide layers to enhance the cycle-to-cycle uniformity in electrochemical metallization cell (ECM) devices.[1–3] Nevertheless, the oxidation of the metal layer at the BL/oxide interface cannot be avoided.[4] This newly formed oxide interfacial layer influences the switching characteristics of the devices, and, thus, the thickness of the BL should be optimized to achieve the desired uniformity.[5] However, these studies[1–5] do not conduct a comparative observation employing various metal layers that could elucidate the origin of such switching modification. In this work, we explore various metals as a barrier layer in the Ag/ZnO/Pt stack ECM cells. We found that the improvement of cycle-to-cycle uniformity found in the devices made with BL is always accompanied by the increase of set voltage variability and the decrease of the memory window. Materials analysis is conducted, and switching mechanisms are proposed to explain this trade-off phenomenon.

Reference
1 D. Panda, F.M. Simanjuntak, S. Chandrasekaran, B. Pattanayak, P. Singh, and T.-Y. Tseng, IEEE Trans. Nanotechnol. 19, 764 (2020).
2 S. Lim, S. Lee, J. Woo, D. Lee, A. Prakash, and H. Hwang, ECS Solid State Lett. 4, Q25 (2015).
3 C.-A. Lin, C.-J. Huang, and T.-Y. Tseng, Appl. Phys. Lett. 114, 093105 (2019).
4 S. Chandrasekaran, F.M. Simanjuntak, T.-L. Tsai, C.-A. Lin, and T.-Y. Tseng, Appl. Phys. Lett. 111, 113108 (2017).
5 S. Chandrasekaran, F.M. Simanjuntak, R. Aluguri, and T. Tseng, Thin Solid Films 660, 777 (2018).

Role of the metal barrier layer in switching characteristics of digitally switched ZnO-based electrochemical metallization cells

ULTRARAM™ is an emerging charge-based memory that is non-volatile whilst also having ultra-low-energy logic-state switching.1,2 These seemingly contradictory properties are achieved by a triple-barrier resonant tunnelling (TBRT) structure, which utilises the extremely large InAs/AlSb conduction band offset (2.1 eV). Much like flash memory, ULTRARAM™ uses a floating gate to store charge, with non-destructive read of the logic state by a proximate channel. However, due to the TBRT structure only 2.5 V is required to program/erase, which is an order of magnitude lower than flash. Switching times and endurance are predicted to be similar to DRAM. ULTRARAM™ has many potential applications including conventional computing (large-scale and personal), artificial intelligence and the internet-of-things. However, for these to be realised, low-cost mass production must be achieved, necessitating growth on 300-mm Si substrates. Growth of III-V’s on Si presents challenges related to differences in lattice constant, thermal expansion coefficients and the polar/non-polar interface. These degrade epilayer quality due to the formation of threading defects and anti-phase domains.3

Here we report on recent progress on the growth of the III-V ULTRARAM™ on Si substrates by molecular beam epitaxy (MBE). A high-quality GaSb surface is required prior to deposition of the In(Ga)As and AlSb memory epilayers. Several growth techniques, including migration-enhanced epitaxy, interface-misfit epitaxy and two-step temperature growth were used to form two different buffer structures on 4˚ offcut substrates: (A) GaSb/GaAs/Ge/Si, where the Ge layer was deposited by chemical vapour deposition, and (B) GaSb/AlSb/Si, where all layers were grown by MBE. A comparison of these buffer layers, as well as a GaSb/GaAs control sample, is shown in the table below. The GaSb/AlSb/Si buffer was found to have the highest quality surface, exceeding that of the control sample grown on GaAs, and was used for growth of the full memory structure (TEM images below). This material has been processed into the first ULTRARAM™ memories on Si, with testing currently underway.

III-V non-volatile ULTRARAM™ memory on Si

Recently, we have successfully employed the single-band tight-binding model to predict the noncollinear spin torque effect in insulator and spin-filter based magnetic tunnel junctions [1]. However, for real complex magnetic heterojunctions, the injected spin-polarized electrons from ferromagnetic electrode can be strongly influenced by the complicated interfacial spin-polarized charge transfer, which is normally ignored in the tight-binding model can causes discrepancy between computational results and experimental findings. 

Our newly developed “JunPy” [2] package has successfully combined the self-consistent Hamiltonian by using the first-principles calculation with the non-equilibrium Green’s function (NEGF) method to obtain the noncollinear spin torque effect in nm-scale magnetic heterojunctions. The divide-and-conquer (DC) method was first applied to reveal the oscillatory decay of layer-resolved spin torques away from the MgO/Fe interface, and suggests a very thin Fe layer thickness below 2 nm to preserve the efficient current-driven magnetization switch [3]. We further developed the Landau-Lifshitz-Gilbert (LLG) equation implemented by our calculated spin transfer torque (STT) effect to simulate the magnetization switching in Fe/MgO/Fe MTJ in the presence of perpendicular magnetic anisotrpy (PMA), external magnetic field, and current-induced spin transfer torque (STT). The resistance as a function of magnetic field (R-H loop) and of bias (R-V loop) are thus obtained and well comparable with experimental results. On the other hand, our “JunPy” package is applied to predict the giant field-like spin torque (FLST) effect in the amine-ended single-molecule magnetic junction [4], which can efficiently assist the molecule scale magnetic proximity effect via interfacial spin filter effect and may open a new avenue for multifunctional manipulation in next-generation organic FLST-MRAMs with lower power consumption. We believe that this newly developed “JunPy” calculation process not only can efficiently resolve current self-consistent difficulties in first-principles calculation for magnetoelectric and magnetotransport properties, but also may inspire future experimental explorations in novel magnetic heterojunctions for spintronics applications. This work is supported by the Ministry of Science and Technology of Taiwan (MOST 107-2633-M-008-004 and 108-2628-M-008-004-MY3).

[1] Y. –H. Tang et al., Phys. Rev. Lett. 103, 057206 (2009); Sci. Rep. 5, 11341 (2015).
[2] https://labstt.phy.ncu.edu.tw/junpy 
[3] B. -H. Huang et al., AIP Advacnes 11, 015036 (2021). This paper was selected as an Editor’s Pick. 
[4] Y. –H. Tang and B. –H. Huang, J. Phys. Chem. C 122, 20500 (2018).


Magnetotransport Properties in Magnetic Heterojunctions: Combined First-Principles Calculation with NEGF Method and Spin Dynamics Simulation

Topological insulators (TI) possess topologically protected surface conducting states and enormous spin-orbit coupling (SOC) [1,2]. This makes TIs ideal candidates for Spin-Orbit Torque (SOT) based Non-volatile Memory. A TI adjacent to a ferromagnetic (FM) thin film generates SOT on the magnetization in FM [2-5] because of Spin Hall Effect (SHE). SOT in TI/FM (ferromagnet) films have been reported previously with TI films epitaxially grown with MBE [2-5], which is not ideal for industrial complementary metal oxide (CMOS) processes. Although, there have been reports of SOT from sputtered TIs [6-8], effects of crystalline disorder in SOT characteristics have not been extensively studied. We performed magnetic and Spin-Torque Ferromagnetic Resonance (ST-FMR) measurements to investigate the effect of sputtering growth temperature and hence crystalline ordering on SOT characteristics of Bi2Te3 coupled with NiFe (Permalloy) and CoFeB as FM layers. The Bi2Te3/FM heterostructures revealed a steady increase in out of plane (OOP) magnetic anisotropy with the increase in crystalline order of Bi2Te3. Further, STFMR measurements revealed a nonlinear trend in damping-like spin orbit torque with increase in sputtering growth temperature. We believe that at room temperature growth, smaller grain size in Bi2Te3 causes quantum-confinement governed enhancement in SOT [6]. However, a giant enhancement in SOT characteristics is observed for highly crystalline c-axis oriented Bi2Te3 heterostructure where Bi2Te3 was grown at 250 ºC. Our results provide a clear path towards integration of crystalline TI based spintronic devices in industrial CMOS compatible processes.

Crystalline Order Dependent Spin-Orbit Torque in Sputter Deposited Topological Insulator /Ferromagnet Heterostructures

With the rapidly growing interest in cryogenic electronics, which is driven by the recent progress in spintronics and quantum / superconducting computing, there is an urgent need to develop logic and memory devices that can operate efficiently at low temperatures. To underpin these new developments there is a need for magnetic semiconductors which are compatible with cryogenic temperatures. We will discuss our recent progress in fabricating exactly these materials.

The rare-earth nitride series offer many intrinsically ferromagnetic semiconductors. They have already been incorporated into prototype field-effect transistors, spin-filters and tunnelling structures. They can be doped by controlling the inclusion of nitrogen vacancies, which donate electrons into the conduction band. They have a finite, and tuneable, conductivity even as the temperature approaches 0 K. Furthermore, the electronic and magnetic properties are not derived from the same electrons, as they are in the dilute magnetic semiconductors, i.e. the saturation magnetization and electron concentration can be tuned independently.

We will show electrical transport and magnetic measurements on GdN and DyN displaying their facility to be doped, along with density functional theory based calculations showing that the dopant states do indeed lie in the conduction band at 0~K. These materials provide cryogenically compatible ferromagnetic semiconductors for application in magnetic memory or spintronics devices.

Ferromagnetic semiconductors for low temperature devices: The rare earth nitrides

The Pt/Hf-based hydroquinone (HQ)/Al2O3/TiN/Si bilayer hybrid memory was prepared by molecular layer deposition (MLD)/atomic layer deposition (ALD). The synthesis of Polymerized hybrid Hf-HQ film is demonstrated by XPS and IR. Free of electroforming process, a typical bipolar resistive switching characteristic has been confirmed with low SET/RESET voltages of -0.85 V/+1.87 V. 8 distinguishable resistance states were obtained, allowing the multi-binary data storage. Long retention time (>104 s) and good switching endurance (2500 times) with ON/OFF ratio around 70 were achieved. The I-V curve of hybrid memory units follows space-charge-limited-current theory, indicating the RS mechanism of conducting filaments. The polymer-like structure of hybrid Hf-HQ can improve the intrinsic flexibility of devices. On the basis, we’ll explore the application of polymerized hybrid Hf-based hydroquinone/Al2O3 bilayer structure in flexible RRAM devices.


Polymerized hybrid Hf-based hydroquinone /Al2O3 bilayer structure by molecular/atomic layer deposition for non-volatile resistive random access memory

Materials that demonstrate high spin-orbit torque are central to the functionality of next-generation spintronic memory and logic technologies. A promising class of materials for this purpose are topological semimetals. While first experimental results have shown the high spin hall angle of Weyl semimetals such as WTe2, these materials are not readily CMOS-compatible and cannot be easily integrated into existing industry-standard cleanroom processes on a 300 mm wafer level. Cobalt silicides are transition metal silicides that are already well-established in the semiconductor industry. Further applications have opened up with the recent identification of cobalt monosilicide (CoSi) as a chiral topological semimetal.

Here, we present material properties of CoSi thin films fabricated on 300 mm wafers using industry-standard cleanroom tools. Metalorganic chemical vapor deposition (MOCVD) was used to deposit Co layers of varied thickness onto wafers with an amorphous Si (a-Si) layer. The stacks were then annealed in the same tool in a vacuum atmosphere. We were able to control the thickness of the fabricated silicide films by adjusting the thickness of the a-Si and deposited Co layers. Relative to the a-Si thickness, the Co thickness was adjusted to obtain silicide films with a 1:1 Co:Si stoichiometry on a nanometer scale. The sensitivity of the composition of the formed silicide to the initial Co to a-Si ratio was investigated using GIXRD. The resistivity of the silicide films was also investigated.

Therefore, we speculate that the CoSi film may possess topological properties for efficient charge-to-spin conversion for use in low-power spintronic applications. This methodology paves the way for fabricating large-scale silicide films on a CMOS platform for spintronic applications.

In vacuo fabrication of thin-film cobalt monosilicide (CoSi) on 300 mm wafer level

ULTRARAM™ is an emerging III-V universal memory that exploits quantum resonant tunnelling to achieve non-volatility and fast, ultralow-low-energy switching per unit area. In this poster, we present characteristics of memories grown on Si substrates which match or exceed recent results for devices grown on GaAs substrates, revealing a path to ULTRARAM™’s commercial viability.

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