Italy

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9204768

**Abstract:**

Analytic doping profiles and contact resistivities are adjusted to reproduce measured transfer characteristics of state-of-the-art n-type and p-type FinFETs by Monte Carlo device simulation. The results are used to compare the performance of nanosheets (NSs) and FinFETs at advanced-node device dimensions. It is found that the ON-current normalized by the effective gate width reduces for a higher number of sheets due to a higher access resistance of the lower-lying sheets. In order to reach the same absolute current level of FinFETs with a fin height of 55 nm, more than two sheets for n-type and about four sheets for the p-type NSs with a NS width of 16 nmare needed, respectively. This technology computer-aided design (TCAD) approach can serve as input for design-technology cooptimization (DTCO) of advanced devices.

ESSCIRC ESSDERC 2021

Monte Carlo Comparison of n-Type and p-Type Nanosheets with FinFETs: Effect of the Number of Sheets

nanosheet

tcad

finfet

monte carlo

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9217.pdf

**Abstract:**

This paper presents a high-bandwidth, high-resolution continuous-time incremental sigma-delta modulator employing a finite impulse response (FIR) filter in the feedback for improved clock jitter immunity. The paper proposes a new scheme to alleviate the aggressive overshoots in the incremental regime. Besides, the presented design features a new implementation technique for the dual-RTZ approach in FIR resistive DACs to eliminate inter-symbol interference (ISI) errors. The presented prototype is fabricated in 180-nm CMOS technology and achieves a dynamic range (DR) of 90.3 dB and a peak spurious-free DR of 93.1 dB at a Nyquist conversion rate of 1 MS/s.

A 93.1-dB SFDR, 90.3-dB DR, and 1-MS/s CT Incremental Sigma-Delta Modulator Incorporating a Resistive Dual-RTZ FIR DAC

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9263.pdf

**Abstract:**

This paper presents a dual-mode, multi-bit, second-order oversampling ADC, which can be configured into Sigma-Delta (SD) mode or Incremental (I) mode for interfacing a single or multiple sensors in multi-sensor platforms for automotive applications. Implemented in a 130-nm CMOS technology, the proposed ADC uses only 0.4µm devices and operates at 2.5-V supply in order to be connected to high-voltage sensors, at the cost of intrinsic lower efficiency. The device achieves a maximum SNDR of 63.0 dB and 56.4 dB in the two modes, respectively, with a bandwidth of 2.1 MHz. By reducing the bandwidth to 1.25 MHz in SD-mode a SNR of 73.2 dB is achieved. In both operating modes, the ADC is clocked at 80 MHz, consuming 2.6 mA.

A Dual-Mode Second-Order Oversampling Analog-to-Digital Converter

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9180.pdf

**Abstract:**

This work presents a scaling-friendly Discrete-Time (DT) 2nd order ΔΣ ADC using a passive switched capacitor (SC) integrator and a novel VCO-Frequency Delta-Sigma Modulator (FDSM). The proposed VCO-FDSM employs a linear VCO with negative feedback. A novel all-digital frequency quantizer quantizes the VCO frequency into a multi-bit output with inherent dynamic element matching (DEM) property, which provides the 1st order mismatch noise shaping in the feedback DAC. The passive SC integrator at the input provides an additional order of noise shaping to the VCO-FDSM. This highly digital architecture facilitates a trade-off between the supply voltage and the operational bandwidth (BW) and makes the design suitable for energy-efficient IoT applications. The test chip fabricated in 65nm CMOS technology operates at the supply voltages ranging from 0.6 V to 1.2 V and achieves a 75.7dB peak SNR in 3.5kHz BW, consuming 7.78 uW with a FoMs of 162.2dB at a 1V supply voltage.

A 0.6-to-1.2 V Scaling Friendly Discrete-Time OTA-Free ΔΣ-ADC for IoT Applications

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9086.pdf

**Abstract:**

This work presents a boost converter with time-based control to reduce the controller area and RHP-zero elimination to increase the maximum bandwidth with no extra off-chip component. A PFM operation with seamless PFM to CCM transition increases the light-load efficiency. The prototype converter, implemented in a BCD technology with 0.18um CMOS, shows a bandwidth increase of factor 5 with respect to a standard boost converter. The measured peak efficiency is 96%. The controller has an area occupation of 0.16 square millimeters with a quiescent current of 300uA.

An 800-mA Time-Based Boost Converter in 0.18µm BCD with Right-Half-Plane Zero Elimination and 96% Power Efficiency

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9295.pdf

**Abstract:**

This paper presents a 40.68MHz active rectifier with cycle-based timing control to extend the allowable duration for completely compensating on/off delays of active diodes under different input voltages and load currents. Both supply-independent ramp and low-voltage-stress startup are also developed to maintain high PCE and VCR and ensure rectifier reliability over a wide input range. Implemented in 0.18um CMOS, the proposed fully-integrated rectifier is the first to achieve full delay compensation at 40.68MHz, so the maximum PCE and VCR reach 86% and 96.3%, respectively, which significantly outperform the prior art.

A 40.68MHz Active Rectifier with Cycle-Based On/Off-Delay Compensation for Biomedical Implants

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9153.pdf

**Abstract:**

This paper introduces a boost controller with Maximum-Power-Point-Tracking for photovoltaic submodule applications. The controller IC operates in constant frequency peak-current-mode control over a wide input voltage range from 7 V - 24 V at output voltages up to 50 V. For light insolation, the converter operates in DCM and uses a variable current pulse height to reduce the switching frequency. The peak efficiency measures 98.4 %, whereas a Maximum-Power-Point tracking efficiency larger 99.9 % is achieved. The current sense is based on a low-side sense resistor, during DCM the inductor current waveform is emulated for precise high-side turn-off.

An Integrated Boost Controller with MPPT for Submodule PV Applications

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9017.pdf

**Abstract:**

We propose a light energy harvester that achieves harvesting efficiency of 82 – 98% at indoor light levels (70 – 1klx) and powers a millimeter-scale system even at 40lx. It improves the efficiency by connecting stacked photovoltaic cells directly to a battery without diode voltage drop and implementing essential battery protection functions in 334pA. The proposed circuit monitors open-circuit voltage of the stacked PV cells indirectly with a tiny auxiliary cell (only 0.16% area penalty) for battery discharging protection without interrupting energy harvesting. It also delays the initial battery charging by 3.9 hours to avoid battery charging during a system assembly process.

A Stacked-Photovoltaic-Cell Energy Harvester with >81% Indoor Light Harvesting Efficiency for Millimeter-Scale Energy-Autonomous Sensor Nodes

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9205844

**Abstract:**

This article focuses on one of the floating body effects in silicon-on-insulator (SOI) substrates, the out-of-equilibrium body potential. Unlike already existing studies which are exploring SOI fully-fabricated devices or SOI wafers measured with pressure probes, here the out-of-equilibrium body potential is explored in SOI substrates with deposited metal contacts. Some technological variants (such as metal choice, annealing, contact geometry) are evaluated through current and potential monitoring under quasi-static conditions. The results of our study reveal a strong dependence of the body potential on the deposited contact material and thermal post-process, while the contact geometry seems to affect less the floating body response.

Out-of-Equilibrium Body Potential Measurement on silicon-on-Insulator with Deposited Metal Contacts

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9174655

**Abstract:**

A new differential method for accurate extraction of electrical parameters of High Electron Mobility Transistor (HEMT) devices for GaN technology is proposed. This method, presented here for the first time, is used to study the mobility degradation with gate length, allowing an analysis of the contribution of the gate edge region to the total MIS-HEMT device conductance. First, an analytical model is proposed to account for the relative conduction of the edges and the main flat part of the channel HEMTs. Second, the differential method allows the split-CV mobility extraction of each part, allowing a precise analysis of the resistive contribution of each region of the HEMT devices. This study has been performed over a large range of channel lengths for two normally-off HEMT GaN wafers having different recess depths.

Analysis of MIS-HEMT Device Edge Behavior for GaN Technology Using New Differential Method

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9186308

**Abstract:**

We investigate the reliability of SiGe HBTs in 55-nm technology under mixed-mode stress. We perform electrical characterization of increased base current degradation at different collector-base voltages. The adopted modeling approach to reproduce experimental data accounts for self-heating and electric fields distribution allowing to match the deviation from the power-law behavior.

Monte Carlo Comparison of n-Type and p-Type Nanosheets with FinFETs: Effect of the Number of Sheets

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Monte Carlo Comparison of n-Type and p-Type Nanosheets with FinFETs: Effect of the Number of Sheets

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